Self-Timed Architecture of a Reduced Instruction Set Computer
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چکیده
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various levels by a CSP-like language. The architectural features include decoupled data and branch processors, delayed branches with variable delay, unified data path and control, efficient non-redundant handshaking protocols, and novel self-timed building blocks such as combinational logic, master-slave registers, finite state machines, and FIFO elements.
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تاریخ انتشار 1993